Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA).  The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm. The results show that the proposed NPLA achieves low power and consumes less than the existing ping lock arbiter

High Performance, Low Power Architectureof 5-stage FIR Filter using ModifiedMontgomery Multiplier

In the field of VLSI, enhancement is promi-nent. Arithmetic circuits are one of the influential sectorsin today’s end products of electronics, where multipliersare one of the deciding factors of efficiency. Multiplierplays an important role in different applications suchas digital signal processing in which it acts as a keyhardware block. As time rolls down, the technologyexposed the ways for the initiation of many hardwareand software implementations of the faster multipliers.One among them is the Montgomery multiplier. Thefundamental operation in the Montgomery multiplier isthe modular multiplication. It is mainly used in FIRfilters, which in-turn has numerous applications suchas speech analysis, multi-rate signal processing, adaptivefilters, and averaging filters. With the usage of proposedcompressor in the conventional design of the multiplier,the number of transistor count has been declined by asignificant amount and made the design into an optimalarea design. This paper presents a modified Montgomerymultiplier design and its implementation in the5thorderFIR filter. The entire design simulation is carried outusing CMOS and PTL logic in 45 nm technology. Thereis an escalation in the result outcomes, and the multiplierhas an area efficiency of 65% and a power reduction ofabout 68% in comparison with conventional design

NEON: Near-accurate efficient FIR Filter for ultra low-power applications

Low-power dissipation is an imperative requirement in the design of an efficient Digital Signal Processing system which is employed in many multimedia applications such as image and video processing. Finite Impulse Response (FIR) filter is indispensable in the design of several such Digital Signal Processing (DSP) applications. The output of these applications, either an image or a video can be nearly accurate for human perception. This toleration in the loss of quality of the output can be exploited to design an energy-efficient system by using approximate computation. Moreover, the efficacy of a system can be improved multi-fold by using reversible logic which benefits in the design of ultra-low-power systems. In this paper, we propose an approximate adder using a reversible Toffoli gate and employ it in designing NEON (Near-accurate and Efficient FIR filter for ultra low-power applicatiONs). Simulation results carried out using Cadence© design tools in 45nm technology node show that the FIR Filter designed using the proposed adder gives significantly better results compared to the designs using the adders in literature. Experiment results using ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the proposed method. In addition to producing fewer garbage outputs, the FIR filter designed using the proposed adder yields power reduction of 74%, delay reduction of 64% and Power-Delay Product reduction of 90.1%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA).  The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm. The results show that the proposed NPLA achieves low power and consumes less than the existing ping lock arbiter